Research and Development

Strategic R&D Initiatives

To launch next-generation products with high added value onto the market in a timely manner, our Corporate Innovation Division leads strategic R&D in collaboration with our development sites and consortiums in Japan and overseas.

R&D Sites

R&D for High NA EUV Technology Toward Practical Application

To support implementation of leading-edge processes using extreme ultraviolet (EUV) technology, we are not only contributing to performance improvements of individual exposure systems, but also positioning integrated process design that includes auxiliary processes such as coating and developing, masking, and measurement and correction, at the core of our R&D. Specifically, we are working to evaluate the performance of photoresists (light-sensitive materials), optimize coater/developer and process conditions, and improve measurement accuracy of fine patterns after exposure. In the coating process, we aim to achieve uniform film thickness through coater/developer control and process parameter optimization. In terms of materials, we are evaluating combinations of high-sensitivity, stable photoresists. To reduce the number of trial runs and improve efficiency of these validations, we are implementing planned experimental design and utilizing digital twin technology and analysis tools.
To support high numerical aperture (High NA) EUV technology, we are evaluating the interactions among reticles, photoresists, and exposure conditions to achieve higher resolution. Specifically, we analyze the effects of wafer patterns on fine patterning, based on data from production equipment and empirical results, and build knowledge for improving mask inspection methods*. By evaluating combinations of optical properties and process responses, we are also working to verify process conditions and equipment control methods that enhance resolution while maintaining throughput.
Over recent years, the major research facilities and leading semiconductor manufacturers around the world have been accelerating adoption of High NA EUV technology as they intensify efforts toward further scaling. In this context, we are focusing on optimization of coating and development, as well as process steps and metrology, in the High NA area. Utilizing data from production equipment and pilot lines, we are validating evaluation methods and equipment control strategies to improve process stability and throughput, while also strengthening our framework to resolve implementation challenges at an early stage through joint research.
In this way, we are enhancing comprehensive support capabilities across materials, equipment, and processes for leading-edge logic and high-density memory beyond the 2 nm nodes, while also enabling further performance improvements through continued scaling.
We are also optimizing the frontend and backend processes of EUV lithography. By taking account of how processes such as film deposition, etching, cleaning affect the final outcome after exposure, we offer approaches to improve yield. We validate these approaches through joint experiments with semiconductor manufacturers, material suppliers, and research institutions, R&D for High NA EUV Technology Toward Practical Application and we proactively work to address potential challenges during mass production.

Mask inspection methods: Technologies for inspecting defects, dimensional accuracy, and misalignment of photomasks used to pattern semiconductor circuit features

Equipment and Process Technologies for Advanced Packaging and Panel-Level Packaging

In semiconductor manufacturing, the importance is increasing of not only feature scaling but also advanced packaging that expands functionality through combinations of multiple chips. We are incorporating advanced technologies developed in deposition, coating/developing, etching, cleaning and other frontend processes, as well as alignment technologies, into our backend equipment. We are also focusing on R&D to enhance reliability of bonding quality, alignment accuracy, and wafer thinning processes. In the area of bonding, we are developing technologies that pre-treat the bonding surfaces to improve bonding strength and electrical connectivity, while also working on process condition optimization to reduce distortion after bonding and equipment design to ensure stable bonding quality. To improve positioning accuracy, in addition to utilizing measurement and analysis technologies such as infrared cameras, high-precision sensors, and image-processing algorithms, we are conducting R&D toward stable high-precision packaging. In the wafer thinning process, we are working to optimize conditions in each process, from back grinding to chemical mechanical polishing (CMP) and edge trimming, to improve yields.
Panel-level packaging has been attracting attention over recent years. While batch production of a large number of packages on large panels is expected to improve productivity, the method also comes with a range of challenges, including panel warping, chip misalignment, and film thickness and wiring uniformity. We are therefore applying panel transfer and warpage correction technologies to achieve uniform coating, and working with material manufacturers and consortiums to confirm suitability for mass production. To improve yields as well, we are working to enhance production efficiency and product reliability by improving screening of good units and thermal management and improving testing accuracy.

Improving Productivity through Panel-level Packaging

Epsira™-centered Acceleration of DX and Innovation

To meet the increased demand driven by the growth of semiconductor fabs, we are developing our Epsira™ DX solutions in a wide range of areas, from R&D to start-up and mass production after installing the equipment at our customers' sites.
In R&D, we are actively utilizing simulation and AI to improve development efficiency. We are also using digital simulations to identify the optimal dimensions and shapes for process stability in the virtual space, prior to prototyping, when designing the chambers of semiconductor production equipment. In this way, we are using simulation and AI to optimize design as we work to minimize prototyping and reduce development lead time. During process development, the increasing complexity and scaling of device structures is dramatically increasing the number of evaluation man-hours and development lead time required for achieving the desired results.
In contrast, we are also adopting process informatics in an effort to minimize experimentation and efficiently achieve our objectives. We are also using materials informatics to search for new materials from among a vast range of candidate materials. We believe that these initiatives will help us achieve a high success rate in development, and reduce environmental impact by reducing the number of prototypes and experiments needed. In addition to developing our own Group DX platform to shorten research and development cycle times, we are also promoting its use and adoption across the entire company.

Epsira™ Development

Shift Left

We are focused on using the Shift Left approach, investing resources such as technology, personnel and expense into the early processes of product development. Through this approach, we are endeavoring to develop various technologies and conducting research for multiple future generations to realize the technology roadmaps we have created with customers.

With product development through the Shift Left approach, we understand customer needs at an earlier stage, reflect the information obtained from feedback into our technological development and propose superior products. This contributes to maximizing yield for customer devices and capacity utilization of their mass production line equipment. We are also promoting on-site collaboration for early delivery of evaluation equipment to customers' fabs and development and research laboratories, and are working to accelerate the process in which technological development is reflected in mass production equipment as well as to optimize development efficiency.

Intellectual Property and Other Intangible Assets

Positioning and Initiatives of Intellectual Property and Intangible Assets

We believe that sustainable growth in the semiconductor industry, where technological innovation is the primary driver of growth, requires strengthening our intellectual property and other intangible assets, including our R&D capabilities and the innovations they generate. We are pursuing R&D utilizing our four strengths (Diagrams (1) to (4)), and we produce innovative and high-value proprietary technologies by actively engaging in collaborations (open innovation) with domestic and international customers, consortiums, and academia, incorporating diverse knowledge and technologies in our R&D. This enables the timely and continuous creation of next-generation equipment, which is the lifeline of our company, and the strategic construction of our patent portfolio (Diagram (5)), which is our fifth strength.
The number of inventions that we created is rising year by year. In 2025, we created 1,415 inventions in Japan and 345 overseas. We have also created almost 300 inventions through partnerships over the past five years. Our global patent application rate has been approximately 75% for seven consecutive years, and in response to the recent growth of the Global South market, we are also increasing the number of applications we submit in these regions. The allowance rate2 of the filed patents was 84% in Japan and 83% in the United States. As of March 31, 2026, we held 26,592 patents, maintaining the No. 1 position in the semiconductor manufacturing equipment industry.

Figures calculated in 2025

TEL Patent Asset Index (PAI*) Trend

We use the Patent Asset Index (PAI) issued by LexisNexis as an indicator of the competitiveness of the patent portfolio The sizes of the circles indicate the size of the patent portfolio, with the PAI of 2016 set to 1.0.

Intellectual Property Governance System

Our intellectual property teams at headquarters and major development sites worldwide collaborate closely with our R&D and business divisions to accurately capture technological advances and market needs and strategically strengthen our intellectual property portfolio. We have also introduced our own inventor recognition program* to encourage the creation of intellectual property. By recognizing inventors at different stages, ranging from those submitting their first patent application to those recognized as outstanding role models, we seek to encourage proactive intellectual property creation and foster a culture of innovation that passes the spirit of invention on to future generations.
Also, Intellectual property activities and intellectual property risks are regularly reported at the Board of Directors meetings and Corporate Officers Meetings. We strive for an even stronger intellectual property governance system through collaboration with management.

"Inventor Prize Program" on our website