Tokyo Electron Introduces CELLESTA™ MS2, a Surface Preparation System
Tokyo Electron (TEL; Head Office: Minato-ku, Tokyo; President: Toshiki Kawai) today announced the launch of the CELLESTA™ MS2, a system for surface preparation and wafer cleaning.
The CELLESTA series of surface preparation systems have been widely adopted by semiconductor manufacturers in single wafer cleaning processes. The newly released CELLESTA MS2 incorporates a physical cleaning function featuring dual-fluid spray technology and brushes. Its capability to process both wafer sides simultaneously significantly boosts the system’s productivity per unit area, making it over 1.5 times more productive than TEL’s existing systems when both wafer sides need to be cleaned. CELLESTA MS2 also helps to reduce the levels of utility usage while processing, because the system eliminates the use of pure water and gases conventionally required to protect the non-washing side of the wafer. Also, TEL’s proprietary wafer retention technology enables the previously challenging task of cleaning the outermost wafer edge and bevel, delivering high levels of particle control required in the manufacture of advanced semiconductors.
“CELLESTA MS2 enables efficient processing of both wafer sides to significantly improve the productivity per unit area, which contributes to footprint reduction,” said Yasuhiro Washio, Vice President & General Manager, CTSPS BU at TEL. “The system also cuts utility usage to reduce the burden on the environment, simultaneously achieving high productivity and low running cost. We will continue to develop innovative technologies and present proposals to better satisfy the needs of our customers.”
* CELLESTA is a registered trademark or trademark of Tokyo Electron Group in Japan and/or other countries.
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PR Group, General Affairs Department, Tokyo Electron