2025 IEEE Symposium on VLSI Technology & Circuits
Event Summary
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Date
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2025.06.08 - 2025.06.12
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Location
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Kyoto, Japan
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Target
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Device Engineer Process Engineer
One of the premier international conferences in semiconductor research, the 2025 IEEE Symposium on VLSI Technology & Circuits, will be held in Kyoto from June 8 to 12!
This international conference covers both device/process technology and circuit technology. At this international conference, where leading experts from the semiconductor industry will gather, Dr. Takaaki Tsunomura from Tokyo Electron (TEL) will serve as the Symposium Chair.
In addition to presenting collaborative papers with the consortium imec, TEL will host a workshop titled "Innovations and Challenges in the Advanced Packaging Era" led by engineer Angelique Raley, who leads technological innovation from the U.S. office of TEL. In this workshop, we will gather industry leaders in EDA, AI Chip design, suppliers, semiconductor production equipment manufacturer, and R&D Consortium to review the recent innovations and trends in advanced packaging and the remaining challenges that need to be overcome across the board to fully leverage the benefits of 3D Scaling.
Get ready for presentations from TEL engineers who are making an impact on the global frontlines!"
#Technology Enabling Life
Regular Workshop 4
Sunday, June 8, 13:00-15:00
Innovations and Challenges in the Advanced Packaging Era
Organizer: A. Raley, TEL Technology Center, America
Technology Session 18 Interconnects
Thursday, June 12, 14:00-15:40
T18-3 - 14:50
Selective Deposition and Ruthenium Superfill Exploration Beyond A10 Node Interconnects
M. van der Veen*, G. Pattanaik**, T. Hakamata**, Y. Otsuki**, A. Romo Negreira**, J. Mayersky**, K. Yu**, R. Yonezawa**, H. Suzuki**, R. Clark**, A. Kumar Mandal*, A. Farokhnejad*, N. Jourdan*, P. Marien* , G. Murdoch*, H. Struyf*, A. Sepulveda Marquez*, S. Park*, J. Swerts* and Z. Tokei*
*imec
**Tokyo Electron
Abstract:
We demonstrate that selective Ru CVD can enable multilayer semi-damascene (SD) interconnects -at the critical metal levels in A10 node and below. In ring oscillator simulations, it is shown that Ru SD flows can benefit from barrierless Ru vias. The Ru CVD has excellent selectivity towards low-k 3.0 in MP21 vias. When Ru vias are combined with Cu wires, the MP24 chain resistance is lower compared to barrierless dual damascene (DD) Ru. Furthermore, we applied Ru superfill CVD in a low-k DD test vehicle at MP21-MP26. The Ru superfill does not induce line bending in SiO2 or in MP21 low-k lines due to its bottomup growth nature. The Ru superfill resistance scaling down to 70 nm2 is confirmed with the physical area. The selective and superfill Ru CVD are enablers of multilayer SD Ru interconnects for future nodes.
