70th Annual IEEE International Electron Devices Meeting (IEDM 2024)
Event Summary
-
Date
-
2024.12.07 - 2024.12.11
-
Location
-
San Francisco| CA
-
Target
-
Device Engineer Process Engineer Data Scientist / Analyst
The world’s largest international conference, the IEEE International Electron Devices Meeting (IEDM), where cutting-edge technological advancements in semiconductor and electronic device technology, design, manufacturing, physics, and modeling are reported, will take place from December 7 to 11 in San Francisco, California! At the conference, Tokyo Electron (TEL) will give a presentation titled “Leading Semiconductor Products and Advanced Packaging”!
Wafer bonding technology, which involves stacking multiple semiconductors made through different processes for device implementation, is gaining attention as an advanced packaging technology such as hybrid bonding. It is expected to further enhance and evolve at the advanced device and system levels, necessitating plasma control technology, cleaning technology, and high-precision alignment technology that are on par with front-end processes. TEL leverages its extensive history of over 60 years to offer equipment that consolidates a wide range of product technologies and innovative eco-solutions aimed at reducing environmental impact.
Get ready for an exciting presentation by the TEL experts!
December 10 5:15 p.m. - 5:40 p.m. PST
Location: Grand Ballroom B
Session #21
Implications of Wafer Bonding for Advanced Logic Technology Development
S. Arkalgud1, C. Netzband1, N. Ip2, A. Tuchman1, Y. Kondo3, I. Son1 and A.Raley1
1. TEL Technology Center, America
2. Tokyo Electron America
3. Tokyo Electron Kyushu
Description
3DI and Heterogenous Integration (HI) have established themselves in the semiconductor industry over the past decade with FPGAs, BSI CMOS Image Sensors, HPC GPUs and High Bandwidth Memory entering volume production. The primary characteristics of 3DI and HI are the use of wafer or die bonding, TSVs and thinning. With these advanced packaging (AP) technologies becoming more mainstream and with device scaling reaching fundamental limits, scaled AP technologies (bonding, thinning, TSV) are now being incorporated into both BEOL and FEOL semiconductor processing to achieve higher performance, bandwidth and/or density. This presentation focuses on the challenges associated with fusion wafer bonding in advanced logic applications.
