October 12, 2021 IR Day Briefing Q&A

Our goal is not to reduce the absolute levels of CO2 emissions, but to reduce “CO2 emissions generated per wafer.” In our Medium-term Environmental Goals for 2030, we are targeting to achieve a 30% reduction in CO2 emissions per wafer, compared to 2018 levels, generated during use of our products. We will achieve this by reducing the power consumption, as well as the amounts of water, chemicals and gases used during use of our products.

Environmental performance has become an important criterion in customer equipment selection. For example, in order to improve wafer output per clean room area unit as required by customers, it is crucial that we improve equipment productivity and yield.
Since improving equipment productivity will lead to the reduction of CO2 emission levels per wafer, the direction of our product development has not changed significantly. In addition, development that incorporates efforts like chemical recycling has become necessary in order to satisfy environmental laws and regulations, or meet different requirements on environmental performance from customers. Collaboration with our partner companies is indispensable toward realizing this development, and is one of the reasons we established the E-COMPASS supply chain initiative.

As scaling continues to 3 nm and then to 2 nm, patterning process costs are expected to grow, but the optimization of process integration will help to control those cost increases. Production technologies are also helping to reduce costs. Please be aware that the capital intensity described on page 101 of the briefing materials is an estimate based on our process assumptions at this point.

In terms of logic, since transistor structure will shift from Fin to Nano sheet, the addition of the gas chemical etch process will increase the number of etch process. We anticipate that deposition and cleaning processes will also increase.
For DRAM, although the pace of node transitions is slowing down, scaling will continue since some immersion ArF exposure processes will be replaced by EUV. We may see a shift from 2D to 3D structures around 2026, which would likely increase the number of processes for deposition and etch.
NAND will continue to see high degrees of integration due to increases in the numbers of layers and tiers. The deposition and etch processes will continue make up a large portion.

If DRAM shifts from 2D to 3D, the processes and necessary equipment will change, potentially causing an inflection. However, 3D DRAM is still in the early stages of technology development, so we cannot yet say with certainty what kind of changes such an inflection will bring.
Other examples include shifts in system integration, such as embedded devices in which memory is embedded on the logic interconnects layer, and hybrid devices that stack logic and memory.

Emerging memory such as ReRAM, PCRAM, and MRAM are primarily being developed as embedded memory. They are also being considered for applications for neuromorphic devices.

According to the imec announcement, the plan is for high-NA EUV lithography equipment to begin operation at the imec-ASML joint high-NA EUV research laboratory in 2023, and for practical applications to start by 2026. We are also advancing our development of coater/developer for high-NA EUV lithography, and contributing to their realization.
Since coater/developer prices vary depending on customers' specifications, I would like to refrain from commenting on them. However, added value will be higher for the coater/developer supporting both CAR (chemically amplified resist) and MOR.
Note that, since EUV lithography processes account for only a limited number of overall manufacturing processes, even if high-NA EUV lithography systems and coater/developer with MOR features are adopted, this will not, by itself, significantly increase customer manufacturing costs.

Our MOR wet resist process approach performs the resist coating, baking and developing processes in a single coater/developer which is connected in-line with EUV lithography system.
On the other hand, the other company’s dry resist process approach performs resist CVD, cleaning, baking, dry etch and then cleaning again, and will therefore require multiple pieces of equipment. As a result, the MOR wet resist process has an advantage in terms of process costs.

Generally speaking, the dry resist process is less likely to cause collapse of resist patterns. Patterns are more likely to collapse in the wet resist process due to surface tension during the development process, but we have introduced new technologies for the rinsing process and in chemical solutions to prevent pattern collapse.

The manufacturing processes for logic 3 nm and 2 nm have not yet been fixed. While scaling tends to make patterning processes more complicated, we are pursuing process integration optimization to control manufacturing costs. As such, we do not expect the number of etch processes to increase significantly in the 3 nm and 2 nm generations, but we do expect the number to increase in conjunction with technology node transitions.

To tighten the incident angle distribution of plasma etch ions, the RF power (high-frequency power) for bias is reduced in frequency, increased in power, and pulsed. Etch process is optimized by combining these three elements.
Customers'requirement is currently an aspect ratio of 70:1, but even higher ratios will be required in the future. We will work toward differentiation of our products utilizing our proprietary technologies.