Q4 FY2024 Earnings Release Conference Q&A
There have been no changes to our CY2025 forecast in the past three months, and we still project the same two-digit growth. Our forecast for CY2025 is that AI-related areas will see particularly strong growth, and we have high hopes for leading-edge logic and memory.
Our sales forecasts are based on investment plans we receive from our customers. At present, we do not expect that those investments for leading-edge and next-generation will be included in our FY2025 NAND sales.
On the other hand, the margin is expected to approximately 47% for H2 FY2025. What is the reason for this profit margin improvement from H1 to H2?
Due cost increases and product mix, gross profit margin for H1 FY2025 will decrease compared to H2 FY2024.
Gross profit margin will improve in H2 FY2025 due to the steady increase of the composition of high value-added products to sales.
Our policy is to conduct R&D that best maximizes our growth potential, so we do not set an upper limit or certain levels for our R&D expense to sales ratio. If we can expect sufficient returns, we will direct more into R&D than we do now.
Looking to our Mid-term Management Plan and beyond, we share technology roadmaps with our customers that include the next four generations. In light of this, if we are presented with an opportunity from which we can expect high returns, and an expansion of high value-added products and SAM*³ that will benefit our customers and our stakeholders, we will invest further in R&D.
As described on page 16 of the briefing materials, our current R&D efforts are focused primarily on cryogenic etching, conductor etching, single wafer ALD, new platform for coater/developer, and leading-edge lithography surface treatment technology. On top of that, in advanced packaging, we would like to further refine our wafer-to-wafer and die-to-wafer bonding technologies, laser lift off technology, and ultra flat wafer manufacturing technology for EUV and for high-density 3D integration, etc.
Our policy is to be flexible when it comes to share buybacks. We decided on 80B yen in share buyback after collectively taking into consideration the market situation, future cash on hand, dividends to shareholders, and the total return amount. We are fully aware that there are many different perspectives when it comes to share price, but we decided to implement the buyback at this time in light of our future growth, and the fact that we can expect to further increase our corporate value.
We have acquired PORs*⁴ for logic interconnect processes.
We expect our cryogenic etching tool to be adopted from 400-layer generation NAND. Small-scale production for 400 layers will begin in CY2025, and mass production in CY2026. Currently, evaluations toward mass production adoption are progressing smoothly. We believe that our technology will begin leveraging an advantage beyond the 400-layer generation not only in terms of process performance, but also from the perspectives of productivity and environmental performance.
We estimate that around 5% of the total coater/developer market may be replaceable by dry resist. We are working on multiple different approaches, but the primary approach we are developing is a special wet method that represents an evolution of conventional methods, focusing on preventing pattern collapse, and it is steadily producing strong results.
There are two types of hybrid bonding. The first is wafer-to-wafer. Our company holds a strong market share in CMOS image sensors. In terms of NAND, we expect that the peripheral circuit bonding process will be established over the next two or three years. Backside PDN*⁵ for logic will be established somewhat later than NAND, and we expect that it will take three to four years. On the other hand, we believe that the second type, die-to-wafer, is still a technology that will be achieved in the future, and we anticipate that the needs for this technology will emerge after those for backside PDN.
By utilizing the diverse technologies we possess, we think that we can provide many differentiated technologies with high added value even in the die-to-wafer area. However, as it may be difficult to tackle all challenges on our own, we are, in fact, considering whether we can collaborate with partner companies to provide our customers with products with high added value as we speak.
Chinese investments are continuing for mature nodes, and we expect to see a similar amount of investment in FY2025 as we did in FY2024. However, as leading-edge investments in other areas will increase, we expect that the sales ratio for China will fall below 40% in FY2025. We feel that there were a small number of rush orders. As for the direction of future regulations, we are not in a position to comment on this matter as a company, and there will be no change in our policy to appropriately respond to the guidelines of the Japanese government, and continue to watch the situation carefully.
WFE (Wafer Fab Equipment): The semiconductor production process is divided into front-end production, in which circuits are formed on wafers and inspected, and back-end production, in which wafers are cut into chips, assembled and inspected again. WFE refers to the production equipment used in front-end production and in wafer-level packaging production.
HARC: High Aspect Ratio Contact
SAM: Served Available Market
POR (Process of Record): Certification of the adoption of equipment in customers' semiconductor production processes
PDN (Power Delivery Network): Design to provide power supply and reference voltage effectively to active devices
FY2024 refers to financial year ending in March 2024.
FY2025 refers to financial year ending in March 2025.
The content above is a summary of the question and answers session.