SPIE. ADVANCED LITHOGRAPHY 2018
Event Summary
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Date
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2018.02.25 - 2018.03.01
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Location
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United States（San Jose）
One of the important technologies to enable the device scaling is lithography. Describing a semiconductor circuit on a silicon wafer precisely is what the lithography does. There is a lot of societies regarding semiconductor. SPIE Advanced Lithography which is sponsored by the International Society for Optical Engineering is one of the very famous societies in the semiconductor lithography area. Currently a variety of technologies is used to describe very fine patterns (a few ten nanometers) in the lithography. Reiterated exposures, pattern transfers to make the feature size smaller, EUV which uses a very short wave length to expose a very small pattern, are being used and will be used in the semiconductor industry. In this society, a lot of presentation of studies is presented and the participants will debate the technology cordially.
Multi-Colors Approach on Self-Aligned Multiple Patterning for Single Line Cut Application
Eric Liu, Akiteru Ko, Richard Farrell, David O’Meara, Chia-Yun Hsieh, Peter Biolsi (TEL Technology Center, America)
Self-Aligned Blocking Integration Demonstration for Critical sub 30nm pitch Mx Level Patterning with EUV self-aligned double patterning
Angélique Raley*2, Joe Lee*1 , Xinghua Sun*2, Richard A. Farrell*2, Jeffrey Shearer*1, Yongan Xu*1 Jeffrey T. Smith*2, Akiteru Ko*2, Andrew W. Metz*2, Peter Biolsi*2, Anton Devilliers*2, John Arnold*1, Nelson Felix*1
*1 Semiconductor Technology Research, IBM Research
*2 Tokyo Electron
New frontiers of atomic layer etching
Sonam D. Sherpa*1, Alok Ranjan*2
*1 TEL Technology Center, America
*2 Tokyo Electron Miyagi
