The fabrication processes (wafer processing and TFT array process) essential for manufacturing semiconductors and TFT-LCDs are similar.
Wafers are placed in a high-temperature furnace. By exposing wafers to a flow of Ox gas, silicon dioxide film is formed on the wafer surfaces. Then silicon nitride film is formed on them by CVD method using silane and ammonia gas.
While the wafers are rotated at a high speed in a coater, they are covered with a uniform coat of photoresist, whose characteristics change when the resist is exposed to ultraviolet (UV) light.
Glass mask with IC patterns on the surface is loaded into the stepper and UV light is applied through the glass mask to the photoresist. The pattern of glass mask is transferred to the photoresist.
In a developer, the wafers are uniformly covered with a developing solution to develop the mask patterns. With positive photoresist, the portion that has been exposed to light becomes soluble, thus leaving the mask patterns on the wafer surfaces.
A plasma dry etch system is used to strip the dielectric films in accordance with the patterns developed on the photoresist. The portion protected by the photoresist remains intact, thus preserving the original pattern structure under the resist.
After etch process, photoresist is removed by Ox plasma. Then wafers are dipped in chemical solvents to remove particles and impurities on the wafer.
Oxide film is deposited in the trenches to form dielectric films. CVD system or SOD coater that applies liquid materials through spinning is used.
Gate film (Ox) is formed by oxidation and plasma nitridation process is applied to the surface of the gate film. Then, gate electrode film (polysilicon) is formed on it by CVD method.
Using the ion implantation machine, the specific elements are implanted into the wafers. And subsequent annealing diffuses these impurities to form source and drain.
Intermetal dielectric film is formed by oxide using CVD method and the film surface is planarized by polishing system subsequently. Contact holes are opened by applying patterning processes to the dielectric film surface.
The holes are filled with metal film by CVD, then excess metal is removed by CMP method.
Low-dielectric-constant film is deposited followed by trench formation in the film by patterning process.Metal films are filled into the trench and excess metals are polished.
Processes from dielectric film formation to metal polishing are repeated to make a multi level inter-connect.
Prober connects the signal node formed tin the LSI chip and the electrical testing machine. Then the failed LSI chips are rejected.