Tokyo Electron Limited (TEL) today announced that the company has begun accepting orders for the CELLESTA+, TELs newest 300mm single wafer cleaning tool. Offering high productivity and optimal performance, the CELLESTA+ represents TELs continuous investment in advanced surface preparation technology.
Based on TELs market-leading coater/developer CLEAN TRACKTM LITHIUS ProTM platform, the CELLESTA+ provides high reliability, process performance and throughput for the most advanced critical cleans for the 45nm technology node and beyond. The advanced single wafer cleaning system has a 12 process spin chamber configuration, enabling a high throughput of 333 wafers per hour. The system also includes two important features to reduce overall system footprint and maximize performance: a new compact spin unit design and onboard chemical supply.
CELLESTA+ has two key features for enabling high performance for next generation critical cleaning applications. Firstly, TEL's original advanced IPA drying technology eliminates the generation of watermarks which are typically associated with HF-last processes and pattern collapse damage that is typically associated with surface tension gradient drying techniques on high aspect ratio features, such as DRAM capacitors. Secondly, CELLESTA+ has an enhanced atomized spray (AS3), which provides a large process window for high particle removal efficiency (PRE) with no pattern or surface structure damage.
With CELLESTA+, TEL offers a complete suite of batch and single wafer surface preparation systems. CELLESTA+ joins the EXPEDIUS+, providing our customers with a range of tooling and process options to meet the increasing challenges faced in the surface preparation processing arena, said Masaaki Hata, VP&General Manager,TEL SPS BU.
1. Maximum throughput of 333 wafers per hour
2. New compact 12 process spin chamber
3. On board chemical supply system
4. TEL original Advanced IPA drying technology with watermarks free
5. Enhanced atomized spray (AS3) for high PRE and no pattern damage
6. High reliability by using TELs Lithography Coater / Developer system wafer handling technology