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5th Stanford and Tohoku Universities
Joint Open Workshop on
3D Transistor and its Applications
Nov. 10th, 2011

  The minimum feature size criterion for LSI is being scaled down aggressively. Eventually, however, this scaling down will reach its limit. The use of 3D is one way to break through that limitation and also increase packing density.

For years, a great deal of attention has been paid to FinFET, memory cell stack and 3D interconnection as innovative technologies that contribute to the continuous growth of the semiconductor industry.

This workshop will discuss not only device technology but also process technology required to realize 3D devices covering the topics listed below.

  • 3D transistors (FinFET, Vertical transistor, Nanowire transistors, others)
  • 3D Memory cell stack technology
  • 3D interconnections
  • Process technologies for 3D devices (Fine pattern delineation, Gate dielectrics, Shallow junction etc.)

Date and Place
Nov. 10th (Thu), 2011. 9:00-16:40
Tohoku University, Tokyo Branch


Program

 Schedule       Title Presenter Affiliation
----------------------------------------------------------------------------------------------------------------------------
  9:00 -  9:20 Opening remark Tetsuo Endoh Tohoku Univ.
  9:20 - 10:10 Evolution from Planar to 3D Nano-Transistors Tahir Ghani Intel
10:10 - 11:00 An Overview of FINFET Technology for 14nm Node High Performance Application Tenko Yamashita IBM
11:00 - 11:15 Break    
11:15 - 12:05 History and Future Trends of 3D DRAM Cell Technology Min-Soo Yoo Hynix
12:05 - 13:30 Lunch     
13:30 - 14:20 Overview of Vertical 3D NAND Flash Memory Technologies Akihiro Nitayama Toshiba
14:20 - 15:10 Application of electro and electroless plating for metal filling in a high aspect ratio TSV Shoso Shingubara Kansai Univ.
15:10 - 15:30 Break     
15:30 - 16:20 TEL's Solution for 3D Devices Tsunetoshi Arikado Tokyo Electron
16:20 - 16:40 Closing remark Yoshio Nishi Stanford Univ.


Website:    http://www.tel.com/eng/seminar/seminar.htm
               

Hosted by:  Yoshio Nishi (Professor, Stanford University), and
                   Tetsuo Endoh (Professor, Tohoku University)

Secretariat:  Tsunetoshi Arikado(TEL), JunkoYabe (TEL)
                    e-mail address:teldepln3dtrworkshop@tel.com
Supported by Tokyo Electron LTD.

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