Trias Ti/TiN CVD, TEL's single wafer CVD system for sub 65nm technology nodes, employs a plasma-free dry-cleaning method in order to eliminate chamber damage and ensure stable operation. The system offers technologically advanced process performance, using a low temperature process that meets the demands of advanced devices, and ALD techniques, such as SFD(Sequential Flow Deposition), which provides the benefits of an ALD-like film without the poor throughput of classic ALD.

• Contact liner barrier - Ti/TiN
• Capacitor electrode - TiN

• Wafer size : 300mm
• Number of process modules : 1 to 4
• Process : pre-clean, Ti deposition, TiN deposition

• *Trias is a registered trademark or a trademark of Tokyo Electron Limited in Japan and other countries.