TOKYO- September 26, 2007-- Tokyo Electron (TEL) today announced that, starting October 1, 2007, the company will begin receiving orders from production fabs throughout the world for the Trias™ High-k CVD system. The new system is a 300mm single-wafer cluster tool designed to produce thin-film materials required for the advanced gate stack, which will be incorporated in the most advanced semiconductor devices at the 45nm node and beyond.

Improvements in transistor speed have historically been accomplished in part by continuously reducing the thickness of the SiO2-based gate insulator through a process known as scaling. However, thinning the gate dielectric to improve transistor speed comes with the price of increased electrical leakage through the dielectric, a factor that negatively impacts power consumption, reliability, and other transistor performance parameters. This has driven an extensive industry-wide effort to develop new, high-permittivity (high-k) insulators to enable continued performance improvements in the nanometer-era of semiconductor devices.

TEL’s Trias High-k CVD system enables the semiconductor industry to realize the promise of high-k dielectrics by combining highly-specialized 300mm process chambers on a production-proven platform. The heart of the Trias High-k CVD system is TEL’s high-k deposition chamber, which is used to deposit hafnium-based high-k dielectrics. The high-k deposition system is based on TEL’s market-leading single wafer CVD chamber, which incorporates proprietary refinements to optimize film performance.

Complimentary to this chamber is TEL’s UVRF system, a process chamber capable of forming monolayer-scale insulators that serve as the interface between the high-k dielectric and the silicon substrate. These interfacial films are a critical component in the advanced gate stack, and TEL’s UVRF system is unique in its ability to form electrically-sound, highly-uniform films in a production environment. TEL’s SPA and LPA process chambers complete the Trias High-k CVD cluster. These production-proven systems enable the process engineer to refine and optimize the electrical and structural properties of the gate stack through chemical modification and thermal treatment.

The Trias High-k CVD cluster has undergone extensive and rigorous testing at both the component and system level, and has demonstrated excellent reliability and process stability. Process cycle times and mechanical throughput have been optimized to provide efficient, low-cost operation in a high-volume manufacturing environment.


Kenji Washino, Senior Vice President and General Manager of TEL’s Single Wafer Deposition Business Unit, said, “TEL has undertaken an extensive program to develop production-worthy tooling for the advanced gate stack. We have partnered with leading customers and consortia worldwide to develop technology to make the high-k gate stack a reality in production. We are pleased to deliver our Trias High-k CVD systems to our customers who need a high-k gate solution for manufacturing.”

Trias is a trademark of Tokyo Electron Limited in Japan and/or other countries